Category Archives: fpga

Berhubungan dengan FPGA —– Related to FPGA (Field Programmable Gate Array)

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Spartan-3 Starter Kit Board User Guide

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Programming Tools for Altera FPGA — Usb Blaster

If you work with an evaluation board from Altera FPGA, you need a suitable programmer for Altera FPGA. One is a programmer called Usb Blaster is intended only for Altera FPGA.
With Usb Blaster was only using the usb interface with your computer. While the interface to an FPGA using JTAG mode.

This tool would be suitable for all Altera FPGA. To install the drivers, drivers are required to be directed manually to the directory where you installed the program.

Thus you do not need to buy an evaluation board equipped with an internal usb. So you are free to choose the evaluation board or you will work with minimal FPGA and compact.

 

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4digits 7segment display driver: input 4 BCD with blink

 This module is similar to the module that has been in post here. However, this module is not equipped with an internal RAM, so that as the input is 4-digit BCD. Usually this module is used, if the previous modules has registers or RAM which hold data BCD.

In this module has a 4-digit BCD input in parallel. So that the BCD data provided will be displayed to the 4-digit 7segment.

Block of Module

The function of each i / o of this module are:

  • CLK50MHZ is oscillator about 50MHz.
  • BLINK is input control for flashing the 4 digit 7segment display. Active in logic 1.
  • 4 digit BCD input are called as BCD_DIG0..3. Its function is as much as 4-digit bcd input. This 4 digits bcd input is obtained from the previous module connected to this input.
  • Output of SEG(7:0) is used for pattern of 7segment display. Segments of 4 digit usually are connected in parallel.
  • Output of the SEG (3:0) is used to activate each digit of common anode. Because each digit of 7segment will be displayed in scanning method.

 

 

Source code

Testing module

To test the module is not enough if you use the switch on the evaluation board. One way is to use additional modules in the form of a binary counter. The data of counter will be assigned to the output that connected to input of display module.

The following block diagram as a whole to test the module of  “drive7seg_noram_blink”.

Additional modules is called “test_counter” serves as a counter having 4 bcd output. The other used is  library in ISE AND2 to stop the counter because CLK50MHZ on the block if STOP = 0.

Source code of test_counter module

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UART RS232

Serial communication is often used for general applications is RS232. This module is a modification of the module that was created by Dan Pederson, Digileninc, 2004.

Here I made some modifications to the baudrate of the rx / tx can be set manually. Setting baudrate usual through a combination of a switch or a schematic. If you wish to make modifications, please write your profile included in the program comments.

Source code

 

How it works

I will first explain the function of each pin of this module, namely:

  1. BAUD(2:0)
    This pin is 3 bits serves to set baudrate of the TX and RX. There are 8 kinds of combinations baudrate from 000 to 111 are 1200, 2400, 4800, 9600, 19200, 38400, 115200, 115200. Last baudratenya same, so there are only 7 different baudrate. Parity used is odd, 8bits data, stop bit 1.
  2. TX
    This pin is used for transmit data by serially at current baudrate.
  3. RX
    This pin is used for receive data by serially at current barudrate.
  4. CLK
    As base clock at 50MHz.
  5. DBIN
    This pin is used as an 8bits parallel data will bel transmittesd  by serially via the TX pin. This data is provided when TBE = 1 means the bus was empty and ready to accept new data.
  6. DBOUT
    This pin will contain 8bits data has been received by serially via RX pin.  This data will ready if RDA=1.
  7. RDA – Read Data Available
    This pin is used as a flag that the serial data has been received from the RX when RDA=1.
  8. TBE – Transfer Bus Empty
    This pin is used as a flag that the byte to transmit is empty and ready to get a byte again.
  9. RD
    As Read control to get a byte from DBOUT when RDA=1. Active as logic 1.
  10. WR
    As Write control to write a byte to DBIN when TBE=1. Active as logic 1.
  11. PE, FE, OE
    As an indicator of the process of the module.
  12. RST
    As control to reset module and start using baudrate of setting.

Testing

To test this module, additional modules required as a “Top of Module” in ISE. Top module serves to bypass the data from DBOUT sent to DBIN. This means that data is as internal loop. If you use hyperterminal as a tool, then typed data provided in the keyboard will be accepted back as an echo character. Here you will be able to check the function of the module right or wrong.

Source code of top module as follow.

Testing

To test this module, additional modules required as a “Top of Module” in ISE. Top module serves to bypass the data from DBOUT sent to DBIN. This means that data is as internal loop. If you use hyperterminal as a tool, then typed data provided in the keyboard will be accepted back as an echo character. Here you will be able to check the function of the module right or wrong.

Source code of top module as follow.

 

 

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4digits 7segment display driver: with blink

This module is the same as the previous module . This module also serve as a  4 digit  7segment display driver. Module has the distinction is equipped with blinking control lines internally, called “blink”. By providing a logic 1 on this channel, automatically display will flash with a certain period.

How it works

As a display controller 7segmen 4digit led by scanning methods. Scan time to 4 digits is 4x8000x1/50uS = 640uS. Each 7segmen equipped with an internal RAM which can be written using the data bus din [3:0], addr [1:0] and control wr. This RAM contains the BCD data to be displayed to each digit 7segmen.

This module is equipped with an internal oscillator in a blink.  Only by providing a logic 1 on input channel “blink”, the display will flash with a certain period. This would make it simpler to control for the display flashes.

Board Used

 To test the module is used fpga evaluation board Spartan3 XC3S200 from Xilinx. Clock Frequency used is 50MHz. 7segmen displays already available in this board as much as 4 digits. It has been designed featuring a multiplex, because each digit is equipped driver transistor to activate each digit. Led every bit connected in parallel.

 

 

 

Block Architecture

Functional pins can be explained as follows:

  • output digout [3 .. 0] is used to enable every digit of 7segmen displays, active logic 0.
  • seg [7 .. 0] as the display pattern data for forming the digits 0-9 and A-F at 7segment display.
  • addr[1..0] as address bus of internal ram for display bcd buffer.
  • din[3..0] as data bus of internal ram.
  • blink as blink control of display. If blink = 1 the display will flash with a certain period. This is useful for applications that require the display blinking mode, for example, to give warning, the setting for the operator, or other.
  • wr as a control writing of data into ram, active at rising edge. 
  • clk50mhz as clock source.

Controller architecture from 7segment drivers provide blinking using the scanning method is described as follows:

Source Code

 

DEMO

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4digits 7segment display driver: noblink

In the electronic systems are usually required to display the measuring value, setting value, and so forth. Thus the required module to interface displays.  This module is not equipped with blinking internal control input. So, we need externally blinking pulse, blinking oscillator. Externally blinking pulse is usually obtained from the previous module. So that the pulse period can be determined in accordance with the previous module state. This module is the same except have been equipped with blinking control internally.

How it works

As a display controller 7segmen 4digit led by scanning methods. Scan time to 4 digits is 4x8000x1/50uS = 640uS. Each 7segmen equipped with an internal RAM which can be written using the data bus din [3:0], addr [1:0] and control wr. This RAM contains the BCD data to be displayed to each digit 7segmen.

This module is not equipped with an internal oscillator in a blink, blink, so input must be adjusted to a specific frequency through an external oscillator. This module is intended to blink period can be adjusted with the desire.

This module was tested using an evaluation board FPGA from XILINX XC3S200 Spartan3. The frequency of the oscillator used in this evaluation board is 50MHz. To display 4 digits, has been available as 4-digit 7segmen display. This display uss a scanning or multiplex method, because each digit is equipped transistor to turn on each digit of 7segmen display. Every bit segment of 7segmen connected in parallel.

 

 

Block architecture

Functional of pins can be explained as follows:

  • output digout [3 .. 0] is used to enable every digit of 7segmen displays, active logic 0.
  • seg [7 .. 0] as the display pattern data for forming the digits 0-9 and A-F at 7segment display.
  • addr[1..0] as address bus of internal ram for display bcd buffer.
  • din[3..0] as data bus of internal ram.
  • blink as blink control of display. If blink = 1 the display will turn off, blink = 0 the display will turn on. This is useful for applications that require the display blinking mode, for example, to give warning, the setting for the operator, or other.
  • wr as a control writing of data into ram, active at rising edge. 
  • clk50mhz as clock source.

Controller architecture from 7segment drivers using the scanning method is described as follows:

Application Circuit

To apply this module is required circuit 7segmen 4 digit display. To display each digit is switched to logic 0 via the output digout [3 .. 0]. While the pattern formed by the ag segment associated with the output of the module seg [7 .. 0], the remaining segment is the dot. The following image is an electronic circuit at least for the application.

Source code

DEMO

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Programming tools for XILINX FPGA — Platform MultiLINX

Fpga programmer tool MultiLINX Platform provides several modes of programming are: JTAG, Serial and Select MAP. While the interfaces with a computer provided by 2 modes: Serial RS232 and USB. This is a professional programmer and cost more expensive than the Platform Cable USB. However, providing a variety of programming modes and will give you flexibility to program the fpga.

It should be noted, the tool described here is only additional equipment to experiment with the xilinx fpga. This tool is only used as a programmer fpga for xilinx, in order to move the result of the binaries program based your design using fpga development software. Xilinx using ISE , and Altera using Quatrus II as fpga development software. Both hardware (programming tool, the explanation here) and fpga development software should have the right driver (typically been included). Then you are welcome to choose the appropriate board fpga evaluation of your financial ability.

Platform MultiLINX

Using this programming tool, you can freely choose the interface with computers and programming mode with the fpga. But the necessary external power supply is usually obtained from the evaluation board with a voltage of 2.5-5 Volts fpga. Use this to prosesional purposes or financial condition that you have enough to buy it. Provided 4 groups are floating cable, used to serve all existing fpga programming mode. With this floating cable you will easily connect to pin fpga programming. There is a list of labels for the signals in accordance with fpga programming mode. Label numbers correspond to the cable socket.

Have 3 groups of programming mode cables for JTAG, Slave Serial and Select MAP. As you look at sinyal names at box near cables connectors have two header connector are located up and down. At up connector have two groups cables, left for JTG, right for Slave Serial. The bottom connector is used programming for Select MAP mode.  By using this programmer, you do not need to buy an evaluation board equipped fpga programmer internally. Usually the programmer is equipped in the evaluation board with USB interface.

 

 

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How to turn off the 4 digits of 7segment display

On the evaluation board of fpga spartan 3 has 4-digits 7segment display. The displays are usually used to display data or a limited character.

However, for applications that do not require this display, is needed to turn off all digits of 7segment display.  An example is a demo of the application in the post here, the appearance of the 4 digits 7segment can interfere with performance, so need to be turned off.

You need to know the workings of the 7segment 4digits display on the evaluation board of fpga spartan 3, please click here to know it. To turn off all digits of 7segment display is by disabling all common anode of 7segment display. To disable each digit is by setting the common anoda to logic 1, because each digit will active at logic 0.

Common anode pins of 7segment display is called as AN3, AN2, AN1, AN0 with a pin number in sequence are E13, F14, G14, D14.

There are two methods  are behavioral or schematic to turn off all the digits of the 7segment display.

Behavioral

Well I will refer vhdl code posted here. The trick is to add output port for each digit of AN3, AN2, AN1 and AN0 written in Entities Block. To be concise to use array of std_logic.

 

Finally, in Block of process use the initialization as “1111″. Here are excerpts vhdl code then there is the addition, the results become:

 

Finally, in Block of process use the initialization as “1111″. Here are excerpts vhdl code then there is the addition, the results become:

 

Schematic

If you are working on schematic design, you can use schematic editor to disable all 7segment display. Each common anode of 7segment digit must be pulled up to VCC using I/O marker, it’s mean give a logic 1. Next, gave a name each I/O marker, for example as AN0, AN1, AN2 and AN3. 

The following video will describe it:

 

DEMO

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How to design a digital system by a mixture of VHDL and Schematic

Posting this time I plan to redesign the existing digital system that i’ve posted here. Of course, different methods, namely a combination of VHDL and schematic.

And I will explain to you how it works.

Schematic

Schematic above, have a working principle that has been posted here , but designed here is a combination schematic and VHDL modules.

How it works The above schematic can be explained as follows:

  1. STOP input is used to disable CLK50MHZ for passing out to output of AND2 when STOP = 1. When STOP = 1 input module of delay250ms did not get the pulse of CLK50MHZ.
  2. The function of the module delay250ms is to create pulses at the output about 250ms of periode.
  3. The output of addr_count module will move from 00000 to 11111 and vice versa every “rising edge” of input. This output will be as address for the input of led_pattern module. 
  4. The led_pattern pattern module is ROM for leds pattern about 32x8bit of size. This ROM held  binary datas and is defined as an array. 
  5. Q_LED output will be a binary data in accordance with input address of ADDR.
  6. Finally leds will turn on/off according with ROM output.

VHDL Code of Modules

Each module on the schematic above is made in behavioral VHDL and converted to a schematic symbol. Except for INV and AND2 are internal library of the ISE. As the top module constructed schematically as shown in the picture above. The pull up of AN0..AN3 to VCC is used for disable or turned off the 4digits 7segment display. This is up to you.

Module code of delay250ms

Module code of addr_count

 

Module code of led_pattern

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8 leds flasher using pattern look up table

As you can see in this post, the pattern of the 8 leds is only two kinds: turn all leds to off or on. From this post I have an inspiration what if the pattern is stored in a table of ROM or is called  as the look up table (LUT).

Just LED pattern permanently stored in ROM make the LEDs display will have variations. So in this post, the delay time is maintained constant so you can easily understand how it works. But on the other posts will be modified with a delay time that varies.

VHDL Code

 

 

 About the workings of the program above can be explained as follows:

  • Lines 1-3 is definitions of library used. STD_LOGIC_ARITH library contain library of CONV_INTEGER that used in line 36 for converting INTEGER to STD_LOGIC_VECTOR.
  • I / O ports are defined in lines 5-9, STOP to stop flasher, Q_LED to control 8 LED, CLK50MHZ as input timer.
  • Lines 13-23 define the ROM 32x8bits for the pattern of the LED display is called “led_lut”. LUT was marked by the addresses 0-31 or 00000 to 11111 in binary. As marker addresses of LUT is addr_lut and the defining is line 26. 
  • Lines 25-26 are defining of variable dly as delay counter and addr_lut as a marker addresses of LUT. 
  • Lines 31-44 are block of process.
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Simple 8 leds flasher with options delay

Examples of programs here is same with the previous example, just added the option of delay using combination of switchs. Consists of two switches that are used to select the delays. The combination switch will determine a constant delay that is stored in the ROM table as a reference delay at this time. 

VHDL Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The line by line explanations of vhdl codes as follow:

  • Lines 1-4 is the definition of libraries used.
  • Lines 6-12 is the definition of I/O channels used. STOP is input channel for stopping leds flashing or all leds will turned off. DLY_OPT is used to select the time of delay that held in ROM tables called as romdelay. Q_LED is array channel outputs for driving 8 leds. CLK50MHZ as oscillator clock.
  • Line 16 is the definition of type_romdelay as integer in range 0 to 100000000 or 0 to 2 second.
  • Line 18 is the definition of dly and dly_buff variable as integer in range 0 to 100000000. dly for delay counter and dly_buff as comparing delay assign from romdelay table based on DLY_OPT.
  • Lines 21-27 is  the table of delay selections. 100000000 is 2 second, 50000000 is 1 second, 25000000 is 0.5 second, 12500000 is 0.25 second.
  • Lines 31-50 is the block of process. 
  • Lines 34-39, increment dly as delay counter, if same with dly_buff will read new delay from table, dly reset to zero, make toggle flag_blink.
  • Lines 41-49, turned on leds if STOP=0 and flag_blink=1, if not it leds will turned off.

 

DEMO

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3 to 8 decoder: simple circuit

Here will be explained on the decoder 3 to 8 in a simple. This decoder has 3 inputs and 8 outputs. Input is a binary combination of 0-7, one output will be logic 1 corresponds to the binary input.
The truth table is shown below.

C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

From the truth table above, one utput will be logic 1 depending on the binary input. If the binary input 000 (0 in decimal) output Q0 = 1, other output = 0. If the binary input 101 (5 in decimal) output Q5 = 1, other output = 0. Its means that every single output representing each state of binary inputs. Output is active if logic 1.

Input and output channels each is treated here as channel bits. The block can be described as follows:

3 to 8 decoder: non array

Block of decoder on the left is illustrated with line input and output separately for every bit.  Actually this way is intended to clarify that the required programming ideas in simple writing program. Programming here does not consider the efficient programming techniques. It aims to provide a lot of consideration and show that efficient programming is with a simple description.

Another explanation, the input and output channels will be treated as arrays. So that would seem programming will be easier and simpler.

Entities blocks can be written as follows:

    entity decoder is
        Port (  A  : in STD_LOGIC;
                B  : in STD_LOGIC;
                C  : in STD_LOGIC;
                Q0 : out STD_LOGIC;
                Q1 : out STD_LOGIC;
                Q2 : out STD_LOGIC;
                Q3 : out STD_LOGIC;
                Q4 : out STD_LOGIC;
                Q5 : out STD_LOGIC;
                Q6 : out STD_LOGIC;
                Q7 : out STD_LOGIC
             );
    End decoder;

Block of the process can be written as follows:

begin
            process (A,B,C)
                begin
                         if A='0' and B='0' and C='0' then
                                     Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0';
                                     Q4<='0'; Q5<='0'; Q6<='0'; Q7<='0';
                         end if;
                         if A='1' and B='0' and C='0' then
                                     Q0<='0'; Q1<='1'; Q2<='0'; Q3<='0';
                                     Q4<='0'; Q5<='0'; Q6<='0'; Q7<='0';
                        end if;
                        if A='0' and B='1' and C='0' then
                                    Q0<='0'; Q1<='0'; Q2<='1'; Q3<='0';
                                    Q4<='0'; Q5<='0'; Q6<='0'; Q7<='0';
                       end if;
                        if A='1' and B='1' and C='0' then
                                    Q0<='0'; Q1<='0'; Q2<='0'; Q3<='1';
                                    Q4<='0'; Q5<='0'; Q6<='0'; Q7<='0';
                       end if;
                       if A='0' and B='0' and C='1' then
                                    Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';
                                    Q4<='1'; Q5<='0'; Q6<='0'; Q7<='0';
                      end if;
                      if A='1' and B='0' and C='1' then
                                   Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';
                                   Q4<='0'; Q5<='1'; Q6<='0'; Q7<='0';
                      end if;
                      if A='0' and B='1' and C='1' then
                                   Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';
                                   Q4<='0'; Q5<='0'; Q6<='1'; Q7<='0';
                     end if;
                     if A='1' and B='1' and C='1' then
                                  Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';
                                  Q4<='0'; Q5<='0'; Q6<='0'; Q7<='1';
                     end if;

end process; 

Because input and output channels are not defined as an array, then the statement in the “process block” can not be written in short.
Furthermore, the input and output channels will be defined as an array. The block can be described as follows:

3 to 8 decoder: array

By treating an array of input and output channels, the program that has the relationship between the data D [3 .. 0] with Q [7 .. 0] will be easily written down and become simpler.

Entities blocks can be written as follows: 

3 to 8 decoder: array

By treating an array of input and output channels, the program that has the relationship between the data D [3 .. 0] with Q [7 .. 0] will be easily written down and become simpler.

Entities blocks can be written as follows:

        entity decoder is
             Port (  D : in STD_LOGIC_VECTOR (2 downto 0);
                     Q : out STD_LOGIC_VECTOR (7 downto 0)
                  );
        end decoder;

The use of the array will cause the writing in “Process Block” to be more simple like the following:

        begin
            With D Select Q
                 "00000001" when "000",
                 "00000010" when "001",
                 "00000100" when "010",
                 "00001000" when "011",
                 "00010000" when "100",
                 "00100000" when "101",
                 "01000000" when "110",
                 "10000000" when others;
DEMO

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Good Luck... 
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Assign I/Os of module into the fpga pins: by writing manually on UCF file

As described in this example, a VHDL program can be as modules that is a black box digital circuits which has input and output channels.  Of course, in practice, the input and output channel of modules need to assign into the fpga pins. This I/Os assigning to fpga pins will be needed for connecting to external circuit like ADC, DAC, Memory, Display, Keyboard or another. To direct the I/Os to the fpga pins need a configuration together with the writing vhdl module. If you use ISE as a fpga developer, this configuration file have file extension  as “.ucf”.

Writing a configuration of .ucf file

One of the easiest ways to redirect i / o in the module to the fpga pins is through the writing of configuration files with extensions UCF.

Figure fpga evaluation board on the left is the Xilinx Spartan 3, click here to see the posting.

In this example, there are 5 channel io module that will be directed to the fpga pins, namely A, B, C, D as input and Q as output. A, B, C, D using 4 switch on the fpga evaluation board in sequence with the pin number are: F12, G12,  H14,  H13. While the Q output is directed to the LED with the pin number: K12.

Thus, to redirect input and output in the module simply by creating a configuration file by writing as follows:

NET “A”         LOC = “F12″ ;

NET “B”        LOC = “G12″ ;

NET “C”        LOC = “H14″ ;

NET “D”        LOC = “H13″ ;

NET “Q”        LOC = “K12″ ;

fpga pin number will depend on the type of fpga evaluation board that you use. Therefore, check data sheet associated with that board.

This configuration file will be compiled jointly if you are on stage by executing “implement design” in the ISE.
You can freely direct i / o of the module that you design to physical pins of the fpga. But you should notice is that the adjustment of the voltage output or input of fpga with external circuit.

The following video explains briefly how to direct i / o of module to fpga pin through the UCF file editor.

DEMO

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Running “Implement Design”

Before executing “implement design”, must first execute the “Synthesize-XST” in the stage design using ISE for Xilinx fpga. Synthesize XST is the phase-compilation that includes checking the syntax and synthesis in accordance with the type of fpga. Furthermore, “the implement Design” is the stage of implementation into the fpga design that includes: Translate, Map and Place & Route.
At this stage UCF files will be compiled together with the module was created (blackbox.vhd). But can also directly execute “implement design”, and when the stage-Synthesize XST not finished it will automatically be executed first. When the stage of Synthesize XST failure, it must be repaired until this stage success.

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Introduction to build a combinational circuit using schematic

The main purpose in posting here is to give an explanation of the introduction to build a digital circuit using schematic. As you can see in this post, a combinational digital circuit has been built  by the behavioral VHDL code with circuit refer to this post.

Sometimes the electronic hobbyist prefer to use shematic method to build a digital circuit.. Perhaps the reason, a more seemingly obvious how it works compared behavioral. However, the behavioral also preferred because it is more compact, especially for complex circuits. But it is also possible to build a complex circuit by combinations of  behavioral and schematic. This method will be more cool and easy to use, because a digital circuit created by behavioral can be converted into block of  schematic and look like a digital component.

I will explain in step by step to create a combinational digital circuit using the existing library of digital gates in the ISE program. Basic to build logic circuits using schematic shown in the following video:

DEMO

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Build a complex digital system using the schematic as a whole is very difficult. ISE permit to build a digital system is a mixture between the Behavioral and Schematic. Each module should be built in behavioral because it can be done in detail. Then each module can be converted to a schematic symbol and will be seen as digital components. Each module is converted to a schematic symbol, you can imagine the result is a digital component in accordance with needs.

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Simple 8 leds flasher

Here I am trying to make a simple program to give an example of using if statements, making the delay, bit toggle flag. To be easily understood, the example here is applied to 8led flasher with a certain period. In block entities, STOP as the input channel in the form of bit, serves to turn off the 8 led. Q_LED an 8bit output channel an array of Q_LED [7 .. 0], serves to turn on or turn off the leds. Internally there is a register for the delay is variable called ‘delay’, serves as a counter delay for the flashing leds. In addition there is a flip-flop bit to mark the led is in a state of on / off is called as “flag_blink”.

VHDL Codes

  • Lines 1-2 are library definitions use standart logic.
  • Lines 4-8 are Entities block define the I/O  of module. STOP as bit input for stopping the flasher. Q_LEDs are outputs as 8bit array for drive 8 leds. And CLK50MHZ as clock about 50MHz.
  • Process block, start on the line 10 and end on the line 36.  
  • Line 12 is a defining a integer for delay counter. Line 13 is defining bit as toggle bit for state of leds blinking.
  • Lines 16-34 is the main process of leds flasher begin by statement “begin”.
  • Below line 18 will be execute only if CLK50MHZ at rising edge state. And lines 19-23 is at the outer loop so that is always executed every CLK50MHZ on rising edge state, which produce the toggle state on flag_blink variable.
  • Lines 24-33 leds will be turned on, only when STOP = 0 and flag_blink = 1.

Flashing period

To calculate the period of the leds flashing is obtained based on frequency oscillator of fpga about 50MHz. With 50MHz oscillator the period become 20 nano second. At line 20 variable flag_blink will be toggled every 2500*8000 count of oscillator period. Time of toggle will be 2500*800*20 nano second =  400,000,000 nano second or 0.4 second. All leds will be turned on about 0.4 second and will be turned of about 0.4 second.

DEMO

YouTube Preview Image

 

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Introduction Verilog: block of program

As mentioned in page about Introduction VHDL, will be described here also another programming language is Verilog or Verilog HDL. Verilog is a programming language by describing hardware as well as computer programming language. For those who are familiar with computer programming languages such as C, Pascal and others could use Verilog to design a fpga.

Block of program is basically same with VHDL, but the programming style is different and almost same as a computer programming language like C. Description of the program block here also refers to those described previously, please click here.

Comment Block course similar to VHDL, especially when using the same software like ISE. Library desciptions block will refer to as the C programming language using the syntax include. Entities and Proccess Block becomes compact as well as the C programming language, written as a function name, arguments and is followed by Proccess Block.

Comment Block course similar to VHDL, especially when using the same software like ISE. Library desciptions block will refer to as the C programming language using the syntax include. Entities and Proccess Block becomes compact as well as the C programming language, written as a function name, arguments and is followed by Proccess Block.

Okay, so as not boring or confusing, I’ll write back in Verilog program as in the previous logic circuit.

module blackbox(A, B, C, D, Q); 

       input A, B, C, D; 
       output Q; assign 

       Q = ~A & ~B & C & D; 
endmodule;

The discussion here is not discussing the “Comment Block”. From the above code, it appears that the Entities Block, Block Proccess into one or compact, because it is a style of computer programming language. Library Descriptions Block can be inserted using include syntax like C programming.

As you can see above the Block Entities beginning with the syntax module:

module blackbox(A, B, C, D, Q);
       input A, B, C, D; 
       output Q;

Or you can be written as follow:

module blackbox(input A, input B, input C, input D, output Q);

Next followed by Proccess Block and should be closed with endmodule syntax, as follow:

      assign Q = ~A & ~B & C & D; 
      endmodule;

Very short and compact, ideal for those who are familiar with computer programming language. But has the disadvantage compared to VHDL. VHDL will be more clearly describe the hardware, making it very easy to be tracked or verified.

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FPGA evaluation board: Altera – Cyclone EP1C6Q240C8

Other vendors who produce FPGA chip, other than XILINX is Altera. Many types are produced Altera and Xilinx, here I will explain the Altera FPGA called the T-Rex C1 Development Kit. FPGA evaluation board has been equipped with several additional components such as buttons, 7segmen displays, VGA port, Serial Port, USB Port, Audio, and even CF Flash Memory.

Additional components are provided for easy to experiment fpga using this board.

 

The TERASIC TREX C1 Development Kit includes the following:

  • TREXC1 development board
  • Altera EP1C6Q240C8
  • Altera EP1S Serial Configuration Device
  • Built-in USB Blaster programming circuitry.
  • Support both JTAG and AS mode programming
  • Option to power via universal serial bus (USB)
  • Eight LEDs
  • Eight Schmitt-trigger de-bounced push buttons
  • 1MByte Flash Memory
  • 8MByte SDRAM (1M x 4 x 16)
  • CF Card Socket (True IDE mode)
  • 16-bit CD-quality Audio DAC with line-out connector
  • TV Encoder with TV Out jack
  • RS-232 Transceiver with 9-pin connector
  • VGA DAC (4-bit resistor network) with VGA-out connector
  • PS2 Keyboard/mouse connector
  • 4-bit DIP switches
  • 4-bit 7-SEG display module
  • Two-40 pin expansion slots.
  • Size?151.5*151.3 mm

Cables and accessories :

  • USB A->B cable (for both USB-blaster programming and the TREX C1 API controll)
  • 7.5V DC Power Supply (We ship UK Plug for Europe/UK areas)
  • Quartus ® II Web Edition design software

 

 

 

 

 

 

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Introduction VHDL: block of program

VHDL is a programming language for fpga design by describing the hardware in the code of program. By using this programming language you can design digital electronics hardware rapidly, then the result of compilation can be embedded into the fpga chip using programmer fpga.

Here I will explain in a simple VHDL programming language by implementing a simple logic circuit to be easily learned. Verilog is also one other programming language that describes hardware. Verilog can be called as Verilog VHDL.

VHDL has many meanings, i checked on the web dictionary, has the following meanings:

 

1 VHDL : Vhsic (Very High Speed Integrated Circuit) Hardware Description Language
2 VHDL : Very High-level Design Language
3 VHDL : Virtual Hardware Description Language
4 VHDL : Very High Density Logic
5 VHDL : Very High Density Lipoprotein

But what is meant here is as enumerated in point 1. Is a programming language for describing hardware in the FPGA chip. Now here VHDL stands for Very high speed integrated circuit Hardware Description Language.

VHDL is a programming language used to develop digital hardware chip embedded into the FPGA About the basic understanding of FPGA click here.

So VHDL can define a programming language (Language) that describes the hardware (Hardware Description) – HDL.  While the V with the addition hsic be Vhsic is “Very high speed integration circuit”, which means that the IC-chip has a high speed. So that VHDL is a programming language to describe hardware in high-speed IC – actually FPGA.

Actually the most important thing is the programming language that describes hardware abbreviated HDL (Hardware Description Language). While VHDL is one of the HDL, the other well known programming languages such as Verilog. Sometimes in order not to be confused, sometimes Verilog called Verilog HDL.

Okay we just concentrate into VHDL ….

Here will be described on VHDL programming structure first.  Then I will provide illustrations of a black box which will be designed in a logic circuit therein.

Black Box of digital circuit

The black box has 4 input channels are named A, B, C and D. And it have 1 output is named Q. Input and outputs have two states called logic 1 (true) and logical 0 (false).

The output Q is determined by the relationship of logic with inputs A, B, C and D.  The relationship of this logic is the logic circuits contained in a black box that will be embedded into FPGA. A, B, C, D and Q is the channel that connects to the FPGA pins.

VHDL program consists of 4 blocks, i call it as: comments block, library descriptions block, i/o description block or entities block, process/logics block.

Program Block of VHDL

Block comments are provided for the programmer as a brief note about the program that has been made. But basically this block is placed on top, but can also be placed in any rows of the program. Block comments placed top line usually gives explanations about:

  1. Company:
    Contains the company name.
  2. Engineer:
    Explaining the name of engineer who contributed to the writing program.
  3. Create Date:
    Explain when the program made. This can be used to determine the age of the program, need to be revised or not.
  4. Design Name:
    It contain the name of the design your program, this is not a unique name but the actual name.
  5. Module Name:
    Here is the module name of your program. The name must be unique and usually the same as the existing name in the program.
  6. Project Name:
    A design usually consists of several program modules, which are combined into one project. In this module needs to be written what the name of the project.
  7. Target Device:
    This module is usually targeted to specific types of fpga chips, so it is necessary to note the name of fpga chips used.
  8. Tool versions:
    To be easily recognizable what tool is used and what version. This is to avoid any error in compilation.
  9. Description:
    A brief explanation is technically about the program module can you write here. Can be a way of working, etc.
  10. Dependencies:
    Usually written program modules that do not stand alone but require other modules. To make it easier to remember should be written the name of the modules required for your modules.
  11. Revision:
    Give the program revision number that you created.
  12. Additional Comments:
    This is just an additional comment that is not covered by other comments.

If you are working on Xilinx fpga using ISE as software development, this form is usually generated automatically when you create new programs.

But, sometimes we do not need to fill the form with descriptions in full as the recommended above. You can fill form with blank character and it is up to you.

I suggest to get used to comment in full, because it is very useful when you create a program that evolved into complex.

So you will easy to identify the program about the revision, relationships with other modules, the workings of the module and so forth. The program would be better if it comes with good documentation, with the aim that the program can be read by others quickly.

Library descriptions block is a describing some libraries that will be used in your program. VHDL compiler like ISE provides many library and should be included in library descriptions block on your program by typing some code. This library contains some functions like mathematical, logic library and etc. Using this library, you do not need to make your own library. In general, these libraries are often used and are fundamental. You have to know what libraries are provided by the library that are included in your program.

Here’s an example of writing to include libraries into your program.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

The first line describes to use the library IEEE in your program. Next line is  explained that all the libraries on STD_LOGIC_1164 will be used. Line 3, line 4 is same but for all of STD_LOGIC_ARITH libray and STD_LOGIC_UNSIGNED library. If you use functions not in the library that is described on this block, will appear an error if the program is compiled.

Entities Block is the description of input and output channels on the ‘black box’ in the image above. This block is intended to describe fully the input and output channels associated with the number of bits, the type i / o ie Input, Output or Bidirectional.

Based on the black box above, can be written as:

entity blackbox is
Port (  A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC );
end blackbox;

Input A, B, C, D are treated as input each 1 bit, a statement as STD_LOGIC. But the 4-bit inputs can be arranged into an array of input or 4-bit bus, for example, expressed as A [3 .. 0], then the description of the entities to be:

entity blackbox is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC );
end blackbox;

Name of modul that described in entities blox is ‘blaxbox’. Entity statement make 4bit bus as inputs named A is written as A [3 .. 0] and output 1bit named Q.

Process Block is a declaration that describes the logic circuits within the black box above. Would thus reflect the workings of the real logic circuits in accordance with the logic input.

What do you want with logic circuits in the black box ?

All that, it’s up to you what you want, of course, limited to the ability of your skills and abilities of the FPGA that you have. There are three choices of logic circuits: combinational, sequential, and the state machine.

This explanation will be easy to learn if combinational logic circuit as choice example. I would chose a simple logic circuit such as logic circuit follow:

An examples of logic circuit in the picture on left, the output Q has a function of inputs A, B, C, D and can be written as:

Q = A’ . B’ . C . D

Simple circuit picture on the left will be embedded into FPGA. In the Process block, described in accordance with the logic circuit by writing the code as follows:

architecture Behavioral of blackbox is

begin

Q <= not A and not B and C and D;

end Behavioral;

In the process block output Q <= not A and not B and C and D. Logic circuits in a black box will depend on the statement in the block this process. when the program is rewritten completely will appear as follows:

———————————————————————————-
– Company:           University of Brawijaya
– Engineer:            Bambang Siswoyo

– Create Date:       05:53:12 12/24/2010
– Design Name:     Example of logic circuit
– Module Name:     blackbox – Behavioral
– Project Name:    diyfpga.com
– Target Devices:   XC3S200-5ft256
– Tool versions:   ISE 10.1
– Description:     An example in combinational logic circuit

– Dependencies:    none

– Revision:
– Revision 0.01 – File Created
– Additional Comments:

———————————————————————————-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity blackbox is
Port (   A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC

             );
end blackbox;

architecture Behavioral of blackbox is

begin

            Q <= not A and not B and C and D;

end Behavioral;

 

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Programming tools for XILINX FPGA — Platform Cable USB

In order to move the result of compiling a binary form, from your circuit design using FPGA, required additional electronic devices as a tool programmers.

The interface between computer and FPGA programming tools can be used any one of such computer interfaces: LPT, Serial RS232, USB and others. In general, many people use usb interface between a USB cable with a computer platform as a data communications. This method is preferred because it uses less cable people.

If you are using Xilinx fpga, binary program can be moved to the evaluation board fpga in two-way: JTAG or Serial. Next, I will explain the programming tools I have for Xilinx fpga namely: Platform Cable USB.

Platform Cable USB

Platform Cable USB is intended for all types of Xilinx fpga and firmware will be updated automatically. Using the USB interface with a computer, making it very simple to use. While the programming mode can be two ways, JTAG and Serial (not RS232).

For JTAG mode using 5 cables for signals is called: TDI, TDO, TCK, TMS and Vref (Aux).

Provided two types of cable: parallel cable and floating cable. Parallel cable can be directly plugged into the header connector on the fpga evaluation board without seeing the name of the signal (cable).

Other things floating cable, provided either JTAG or Serial mode. But you have to be careful when using this type of cable (floating cable), because the signal name of this cable should have the same name between the Platform Cable USB with FPGA evaluation board.

It should be noted, the tool described here is only additional equipment to experiment with the xilinx fpga. This tool is only used as a programmer fpga for xilinx, in order to move the result of  the binaries program based your design using  fpga development software. Xilinx using ISE , and Altera using Quatrus II as fpga development software. Both hardware (programming tool, the explanation here) and fpga development software should have the right driver (typically been included). Then you are welcome to choose the appropriate board fpga evaluation of your financial ability.

For Serial Mode using 6 cables for this signals is called: INIT, DIN, DONE, CCLK, PROG and Vref (Aux).

n the left picture above using a parallel cable only for JTAG mode, you do not need to see the name of the cable signal, but the adjust pin number starting with pin 1. Parallel cable using a ribbon cable for 14 wires. In the right picture above using a floating cable but in JTAG mode, you must carefully about the sinyal name of cables.

Platform Cable USB in action

Complete FPGA development system at least consists of: fpga evaluation boards, fpga software development such as ISE from Xilinx fpga, fpga programmer equipment like the Xilinx Platform Cable USB.

It should be noted that using fpga evaluation board that has a USB communication, usually can be programmed directly without requiring additional programmer tools. However, having equipment fpga programmer, will make you free to choose any kind fpga evaluation board.

Most importantly, the selection of electronic devices submitted to you, of course, tailored to your financial condition.

 

 

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FPGA evaluation board: XILINX Spartan 3 – XC3S200

If you will prepare to learn the FPGA, you need a FPGA evaluation board from various vendors such as Xilinx, Altera, Actel, and so on.

The evaluation board contains the FPGA chips typically according to your choice and consists of other supporting components such as RAM, EEPROM, 7Segmen Display, buttons, connectors, aims to facilitate learning.

The author gives suggestions for using an FPGA evaluation board is the cheapest for the first time experimenting in FPGA applications, such as the spartan 3.

The author used an evaluation board from Xilinx Spartan 3  which has specifications:

  1. Xilinx Spartan-3 FPGA – XC3S200 w/ twelve 18-bit multipliers, 216Kbits of block RAM, and up to 500MHz internal clock speeds
  2. On-board 2Mbit Platform Flash (XCF02S)
  3. 8 slide switches, 4 pushbuttons, 9 LEDs, and 4-digit seven-segment display
  4. Serial port, VGA port, and PS/2 mouse/keyboard port
  5. Three 40-pin expansion connectors
  6. Three high-current voltage regulators (3.3V, 2.5V, and 1.2V)
  7. Works with Digilent’s JTAG3, JTAG USB, and JTAG USB Full Speed cables, as well as P4 & MultiPRO cables from Xilinx
  8. 1Mbyte on-board 10ns SRAM (256Kb x 32)

To experiment fpga, the first, you must have an evaluation board fpga accordance with your financial abilities. Use a cheap price to learn first, then buy a high-priced in accordance with the development of your skills.

  

Technical explanations of the FPGA evaluation board

I will try to explain the technical of this evaluation board, may be useful for you to experiment on fpga.The technical explanations are based on the specifications of the fpga evaluation board above.

To connect the digital signal between the evaluation board with digital circuits outside board, provided the pins as the digital interface on the evaluation board as follows:

Digitally Interfaces

Expansion connectors

This evaluation module need additional equipment in the form of programmer via jtag connector. For the purposes of digitally interfaces with the external circuits, provided 32×3 = 96 bits I /O through 3 expansion connectors namely A1, A2 and B1. 96-bit I / Os are freely used for digital interfaces such as ADC, DAC, LCD, serial / parallel communications, etc. A voltage level that is used I / O’s FPGA must be the same voltage level that is used I/O’s circuits outside the FPGA. In general, the voltage level of I / O’s FPGA used is 3.3 Volt. You need to match this level voltage using a resistor connected in series.

8 switches

8 switchs can be used as an alternative of the digital input, can changed as toggle to logic 0 or 1. Usually, this switchs are used as input logic to combination logic circuit or a sequential logic circuit.

4 buttons

This is the same button switch ’8 switches’, just not a toggle, if pressed will be a logic 0, if released will be a logic 1. This button is provided if the input logic circuits require a logic transition, such as the input of the sequence logic circuit. Essentially, use this buttons if you need input as a pulse by pressing manually the button.

8 LEDs

8 LEDs are typically used as an indicators in your application design. Or to visually test the digital output, if you are still in early stages of experimenting. So LEDs that have been included in this fpga module will helpful for you in the experiment without having to soldering or connecting the LEDs to the pins of the FPGA.

Standard interfaces

Specially interface is provided for standard interfaces such as RS232, VGA port, port PS/2. This standard interface commonly used for standard devices such as keyboards using P/S 2 interface, the monitor uses a VGA port interface, RS232 (serial terminal) using serial port interface. This interface can be applied in accordance with the design you have.

 

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