Introduction VHDL: block of program

VHDL is a programming language for fpga design by describing the hardware in the code of program. By using this programming language you can design digital electronics hardware rapidly, then the result of compilation can be embedded into the fpga chip using programmer fpga.

Here I will explain in a simple VHDL programming language by implementing a simple logic circuit to be easily learned. Verilog is also one other programming language that describes hardware. Verilog can be called as Verilog VHDL.

VHDL has many meanings, i checked on the web dictionary, has the following meanings:

 1 VHDL : Vhsic (Very High Speed Integrated Circuit) Hardware Description Language 2 VHDL : Very High-level Design Language 3 VHDL : Virtual Hardware Description Language 4 VHDL : Very High Density Logic 5 VHDL : Very High Density Lipoprotein

But what is meant here is as enumerated in point 1. Is a programming language for describing hardware in the FPGA chip. Now here VHDL stands for Very high speed integrated circuit Hardware Description Language.

VHDL is a programming language used to develop digital hardware chip embedded into the FPGA About the basic understanding of FPGA click here.

So VHDL can define a programming language (Language) that describes the hardware (Hardware Description) – HDL.  While the V with the addition hsic be Vhsic is “Very high speed integration circuit”, which means that the IC-chip has a high speed. So that VHDL is a programming language to describe hardware in high-speed IC – actually FPGA.

Actually the most important thing is the programming language that describes hardware abbreviated HDL (Hardware Description Language). While VHDL is one of the HDL, the other well known programming languages such as Verilog. Sometimes in order not to be confused, sometimes Verilog called Verilog HDL.

Okay we just concentrate into VHDL ….

Here will be described on VHDL programming structure first.  Then I will provide illustrations of a black box which will be designed in a logic circuit therein.

Black Box of digital circuit

The black box has 4 input channels are named A, B, C and D. And it have 1 output is named Q. Input and outputs have two states called logic 1 (true) and logical 0 (false).

The output Q is determined by the relationship of logic with inputs A, B, C and D.  The relationship of this logic is the logic circuits contained in a black box that will be embedded into FPGA. A, B, C, D and Q is the channel that connects to the FPGA pins.

VHDL program consists of 4 blocks, i call it as: comments block, library descriptions block, i/o description block or entities block, process/logics block.

Program Block of VHDL

Block comments are provided for the programmer as a brief note about the program that has been made. But basically this block is placed on top, but can also be placed in any rows of the program. Block comments placed top line usually gives explanations about:

1. Company:
Contains the company name.
2. Engineer:
Explaining the name of engineer who contributed to the writing program.
3. Create Date:
Explain when the program made. This can be used to determine the age of the program, need to be revised or not.
4. Design Name:
It contain the name of the design your program, this is not a unique name but the actual name.
5. Module Name:
Here is the module name of your program. The name must be unique and usually the same as the existing name in the program.
6. Project Name:
A design usually consists of several program modules, which are combined into one project. In this module needs to be written what the name of the project.
7. Target Device:
This module is usually targeted to specific types of fpga chips, so it is necessary to note the name of fpga chips used.
8. Tool versions:
To be easily recognizable what tool is used and what version. This is to avoid any error in compilation.
9. Description:
A brief explanation is technically about the program module can you write here. Can be a way of working, etc.
10. Dependencies:
Usually written program modules that do not stand alone but require other modules. To make it easier to remember should be written the name of the modules required for your modules.
11. Revision:
Give the program revision number that you created.
This is just an additional comment that is not covered by other comments.

If you are working on Xilinx fpga using ISE as software development, this form is usually generated automatically when you create new programs.

But, sometimes we do not need to fill the form with descriptions in full as the recommended above. You can fill form with blank character and it is up to you.

I suggest to get used to comment in full, because it is very useful when you create a program that evolved into complex.

So you will easy to identify the program about the revision, relationships with other modules, the workings of the module and so forth. The program would be better if it comes with good documentation, with the aim that the program can be read by others quickly.

Library descriptions block is a describing some libraries that will be used in your program. VHDL compiler like ISE provides many library and should be included in library descriptions block on your program by typing some code. This library contains some functions like mathematical, logic library and etc. Using this library, you do not need to make your own library. In general, these libraries are often used and are fundamental. You have to know what libraries are provided by the library that are included in your program.

Here’s an example of writing to include libraries into your program.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

The first line describes to use the library IEEE in your program. Next line is  explained that all the libraries on STD_LOGIC_1164 will be used. Line 3, line 4 is same but for all of STD_LOGIC_ARITH libray and STD_LOGIC_UNSIGNED library. If you use functions not in the library that is described on this block, will appear an error if the program is compiled.

Entities Block is the description of input and output channels on the ‘black box’ in the image above. This block is intended to describe fully the input and output channels associated with the number of bits, the type i / o ie Input, Output or Bidirectional.

Based on the black box above, can be written as:

entity blackbox is
Port (  A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC );
end blackbox;

Input A, B, C, D are treated as input each 1 bit, a statement as STD_LOGIC. But the 4-bit inputs can be arranged into an array of input or 4-bit bus, for example, expressed as A [3 .. 0], then the description of the entities to be:

entity blackbox is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
Q : out STD_LOGIC );
end blackbox;

Name of modul that described in entities blox is ‘blaxbox’. Entity statement make 4bit bus as inputs named A is written as A [3 .. 0] and output 1bit named Q.

Process Block is a declaration that describes the logic circuits within the black box above. Would thus reflect the workings of the real logic circuits in accordance with the logic input.

What do you want with logic circuits in the black box ?

All that, it’s up to you what you want, of course, limited to the ability of your skills and abilities of the FPGA that you have. There are three choices of logic circuits: combinational, sequential, and the state machine.

This explanation will be easy to learn if combinational logic circuit as choice example. I would chose a simple logic circuit such as logic circuit follow:

An examples of logic circuit in the picture on left, the output Q has a function of inputs A, B, C, D and can be written as:

Q = A’ . B’ . C . D

Simple circuit picture on the left will be embedded into FPGA. In the Process block, described in accordance with the logic circuit by writing the code as follows:

architecture Behavioral of blackbox is

begin

Q <= not A and not B and C and D;

end Behavioral;

In the process block output Q <= not A and not B and C and D. Logic circuits in a black box will depend on the statement in the block this process. when the program is rewritten completely will appear as follows:

———————————————————————————-
– Company:           University of Brawijaya
– Engineer:            Bambang Siswoyo

– Create Date:       05:53:12 12/24/2010
– Design Name:     Example of logic circuit
– Module Name:     blackbox – Behavioral
– Project Name:    diyfpga.com
– Target Devices:   XC3S200-5ft256
– Tool versions:   ISE 10.1
– Description:     An example in combinational logic circuit

– Dependencies:    none

– Revision:
– Revision 0.01 – File Created

———————————————————————————-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity blackbox is
Port (   A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC

);
end blackbox;

architecture Behavioral of blackbox is

begin

Q <= not A and not B and C and D;

end Behavioral;

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