# Introduction Verilog: block of program

As mentioned in page about Introduction VHDL, will be described here also another programming language is Verilog or Verilog HDL. Verilog is a programming language by describing hardware as well as computer programming language. For those who are familiar with computer programming languages such as C, Pascal and others could use Verilog to design a fpga.

Block of program is basically same with VHDL, but the programming style is different and almost same as a computer programming language like C. Description of the program block here also refers to those described previously, please click here.

Comment Block course similar to VHDL, especially when using the same software like ISE. Library desciptions block will refer to as the C programming language using the syntax include. Entities and Proccess Block becomes compact as well as the C programming language, written as a function name, arguments and is followed by Proccess Block.

Comment Block course similar to VHDL, especially when using the same software like ISE. Library desciptions block will refer to as the C programming language using the syntax include. Entities and Proccess Block becomes compact as well as the C programming language, written as a function name, arguments and is followed by Proccess Block.

Okay, so as not boring or confusing, I’ll write back in Verilog program as in the previous logic circuit.

module blackbox(A, B, C, D, Q);

input A, B, C, D;
output Q; assign

Q = ~A & ~B & C & D;
endmodule;

The discussion here is not discussing the “Comment Block”. From the above code, it appears that the Entities Block, Block Proccess into one or compact, because it is a style of computer programming language. Library Descriptions Block can be inserted using include syntax like C programming.

As you can see above the Block Entities beginning with the syntax module:

module blackbox(A, B, C, D, Q);
input A, B, C, D;
output Q;


Or you can be written as follow:

module blackbox(input A, input B, input C, input D, output Q);


Next followed by Proccess Block and should be closed with endmodule syntax, as follow:

      assign Q = ~A & ~B & C & D;
endmodule;


Very short and compact, ideal for those who are familiar with computer programming language. But has the disadvantage compared to VHDL. VHDL will be more clearly describe the hardware, making it very easy to be tracked or verified.

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