Posting this time I plan to redesign the existing digital system that i’ve posted here. Of course, different methods, namely a combination of VHDL and schematic.
And I will explain to you how it works.
Schematic above, have a working principle that has been posted here , but designed here is a combination schematic and VHDL modules.
How it works The above schematic can be explained as follows:
- STOP input is used to disable CLK50MHZ for passing out to output of AND2 when STOP = 1. When STOP = 1 input module of delay250ms did not get the pulse of CLK50MHZ.
- The function of the module delay250ms is to create pulses at the output about 250ms of periode.
- The output of addr_count module will move from 00000 to 11111 and vice versa every “rising edge” of input. This output will be as address for the input of led_pattern module.
- The led_pattern pattern module is ROM for leds pattern about 32x8bit of size. This ROM held binary datas and is defined as an array.
- Q_LED output will be a binary data in accordance with input address of ADDR.
- Finally leds will turn on/off according with ROM output.
VHDL Code of Modules
Each module on the schematic above is made in behavioral VHDL and converted to a schematic symbol. Except for INV and AND2 are internal library of the ISE. As the top module constructed schematically as shown in the picture above. The pull up of AN0..AN3 to VCC is used for disable or turned off the 4digits 7segment display. This is up to you.
Module code of delay250ms
Module code of addr_count
Module code of led_pattern
Last updated byat .