As described in this example, a VHDL program can be as modules that is a black box digital circuits which has input and output channels. Of course, in practice, the input and output channel of modules need to assign into the fpga pins. This I/Os assigning to fpga pins will be needed for connecting to external circuit like ADC, DAC, Memory, Display, Keyboard or another. To direct the I/Os to the fpga pins need a configuration together with the writing vhdl module. If you use ISE as a fpga developer, this configuration file have file extension as “.ucf”.
One of the easiest ways to redirect i / o in the module to the fpga pins is through the writing of configuration files with extensions UCF.
Figure fpga evaluation board on the left is the Xilinx Spartan 3, click here to see the posting.
In this example, there are 5 channel io module that will be directed to the fpga pins, namely A, B, C, D as input and Q as output. A, B, C, D using 4 switch on the fpga evaluation board in sequence with the pin number are: F12, G12, H14, H13. While the Q output is directed to the LED with the pin number: K12.
Thus, to redirect input and output in the module simply by creating a configuration file by writing as follows:
NET “A” LOC = “F12″ ;
NET “B” LOC = “G12″ ;
NET “C” LOC = “H14″ ;
NET “D” LOC = “H13″ ;
NET “Q” LOC = “K12″ ;
fpga pin number will depend on the type of fpga evaluation board that you use. Therefore, check data sheet associated with that board.
This configuration file will be compiled jointly if you are on stage by executing “implement design” in the ISE.
You can freely direct i / o of the module that you design to physical pins of the fpga. But you should notice is that the adjustment of the voltage output or input of fpga with external circuit.
The following video explains briefly how to direct i / o of module to fpga pin through the UCF file editor.
Running “Implement Design”
Before executing “implement design”, must first execute the “Synthesize-XST” in the stage design using ISE for Xilinx fpga. Synthesize XST is the phase-compilation that includes checking the syntax and synthesis in accordance with the type of fpga. Furthermore, “the implement Design” is the stage of implementation into the fpga design that includes: Translate, Map and Place & Route.
At this stage UCF files will be compiled together with the module was created (blackbox.vhd). But can also directly execute “implement design”, and when the stage-Synthesize XST not finished it will automatically be executed first. When the stage of Synthesize XST failure, it must be repaired until this stage success.
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