This module is the same as the previous module . This module also serve as a 4 digit 7segment display driver. Module has the distinction is equipped with blinking control lines internally, called “blink”. By providing a logic 1 on this channel, automatically display will flash with a certain period.
How it works
As a display controller 7segmen 4digit led by scanning methods. Scan time to 4 digits is 4x8000x1/50uS = 640uS. Each 7segmen equipped with an internal RAM which can be written using the data bus din [3:0], addr [1:0] and control wr. This RAM contains the BCD data to be displayed to each digit 7segmen.
This module is equipped with an internal oscillator in a blink. Only by providing a logic 1 on input channel “blink”, the display will flash with a certain period. This would make it simpler to control for the display flashes.
To test the module is used fpga evaluation board Spartan3 XC3S200 from Xilinx. Clock Frequency used is 50MHz. 7segmen displays already available in this board as much as 4 digits. It has been designed featuring a multiplex, because each digit is equipped driver transistor to activate each digit. Led every bit connected in parallel.
- output digout [3 .. 0] is used to enable every digit of 7segmen displays, active logic 0.
- seg [7 .. 0] as the display pattern data for forming the digits 0-9 and A-F at 7segment display.
- addr[1..0] as address bus of internal ram for display bcd buffer.
- din[3..0] as data bus of internal ram.
- blink as blink control of display. If blink = 1 the display will flash with a certain period. This is useful for applications that require the display blinking mode, for example, to give warning, the setting for the operator, or other.
- wr as a control writing of data into ram, active at rising edge.
- clk50mhz as clock source.
Controller architecture from 7segment drivers provide blinking using the scanning method is described as follows:
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