In the electronic systems are usually required to display the measuring value, setting value, and so forth. Thus the required module to interface displays. This module is not equipped with blinking internal control input. So, we need externally blinking pulse, blinking oscillator. Externally blinking pulse is usually obtained from the previous module. So that the pulse period can be determined in accordance with the previous module state. This module is the same except have been equipped with blinking control internally.
How it works
As a display controller 7segmen 4digit led by scanning methods. Scan time to 4 digits is 4x8000x1/50uS = 640uS. Each 7segmen equipped with an internal RAM which can be written using the data bus din [3:0], addr [1:0] and control wr. This RAM contains the BCD data to be displayed to each digit 7segmen.
This module is not equipped with an internal oscillator in a blink, blink, so input must be adjusted to a specific frequency through an external oscillator. This module is intended to blink period can be adjusted with the desire.
This module was tested using an evaluation board FPGA from XILINX XC3S200 Spartan3. The frequency of the oscillator used in this evaluation board is 50MHz. To display 4 digits, has been available as 4-digit 7segmen display. This display uss a scanning or multiplex method, because each digit is equipped transistor to turn on each digit of 7segmen display. Every bit segment of 7segmen connected in parallel.
Functional of pins can be explained as follows:
- output digout [3 .. 0] is used to enable every digit of 7segmen displays, active logic 0.
- seg [7 .. 0] as the display pattern data for forming the digits 0-9 and A-F at 7segment display.
- addr[1..0] as address bus of internal ram for display bcd buffer.
- din[3..0] as data bus of internal ram.
- blink as blink control of display. If blink = 1 the display will turn off, blink = 0 the display will turn on. This is useful for applications that require the display blinking mode, for example, to give warning, the setting for the operator, or other.
- wr as a control writing of data into ram, active at rising edge.
- clk50mhz as clock source.
Controller architecture from 7segment drivers using the scanning method is described as follows:
To apply this module is required circuit 7segmen 4 digit display. To display each digit is switched to logic 0 via the output digout [3 .. 0]. While the pattern formed by the ag segment associated with the output of the module seg [7 .. 0], the remaining segment is the dot. The following image is an electronic circuit at least for the application.
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